Lead frame, semiconductor device, and method for manufacturing semiconductor device

ABSTRACT

In a lead frame used in a molded package of a semiconductor device, leads disposed entirely including an island portion, which is a portion for mounting a semiconductor chip, are formed. In the manufacture of a semiconductor device, after mounting the semiconductor chip and performing wire bonding and resin sealing, the leads are adequately cut corresponding to the number of electrodes of the semiconductor chip to divide the leads into a plurality of portions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a lead frame, a semiconductor device,and a method for manufacturing a semiconductor device. Morespecifically, the present invention relates to a lead frame used in themolded package of a semiconductor integrated circuit, a semiconductordevice using such a lead frame, and a method for manufacturing such asemiconductor device.

2. Background Art

Presently, various types of surface-mounted packages are used insemiconductor devices. One of the surface-mounted packages is a packageknown as a QFN (quad flat non-leaded package).

A QFN has no lead pins on the four sides thereof, and a lead frame,which becomes external terminals, is exposed on the bottom surface ofthe semiconductor device. Therefore, the QFN is superior to a QFP (quadflat package) having lead pins on the four sides in both the mountablearea and the height. The QFN is also advantageous because a plurality ofsemiconductor chips can be mounted.

In recent years, however, increase in the number of external terminalshas been demanded to cope with increase in the number of pins of asemiconductor chip. Therefore, various techniques to increase the numberof leads in a lead frame have been proposed also for QFNs.

In QFNs, however, leads are arrayed in the peripheral portions of thebottom surface of a semiconductor device outside the ofsemiconductorchip. Therefore, if thenumberof external terminals isincreased, the size of the entire semiconductor device must be enlarged.

SUMMARY OF THE INVENTION

Therefore, the present invention is intended to solve theabove-described problems, and to provide a lead frame, a semiconductordevice, and a method for manufacturing a semiconductor device that cansecure a required number of external terminals corresponding to thenumber of terminals in the semiconductor device, while suppressing theenlargement of the package.

According to one aspect of the present invention, a lead frame used inthe mold package of a semiconductor device, comprises a lead to beterminals in the semiconductor device. The lead can be divided bycutting into a plurality of parts that can be used as terminals.

According to another aspect of the present invention, a semiconductordevice comprises a semiconductor chip, a lead frame, gold wires and asealing member. The semiconductor chip has a plurality of bonding pads.The lead frame mounts the semiconductor chip, and includes a lead tobecome terminals in the semiconductor device. The gold wireselectrically connect the bonding pads to predetermined locations of thelead. The sealing member seals the semiconductor chip on the lead frame.The lead is divided into a predetermined number at predeterminedlocations after mounting the semiconductor chip, and are used asindividual terminals corresponding to the bonding pads in a one-to-onemanner.

According to another aspect of the present invention, in a method formanufacturing a semiconductor device, a semiconductor chip that has aplurality of bonding pads is mounted on a predetermined location of alead frame. The bonding pads are connected to a lead of the lead frameby a gold wire. The semiconductor chip is sealed on the lead frame usinga sealing member. The lead frame is cut on the predetermined location todivide the lead into individual terminals corresponding to the bondingpads in a one-to-one manner.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1A and 1B are schematic diagrams for illustrating a semiconductordevice 100 in the first embodiment of the present invention;

FIG. 2 is a schematic top view for illustrating a lead frame 110 used inthe semiconductor device 100 in the first embodiment of the presentinvention;

FIG. 3 is a flow diagram for illustrating the method for manufacturing asemiconductor device 100 according to the first embodiment of thepresent invention;

FIGS. 4A to 7B are schematic diagrams for illustrating the state of thesemiconductor device 100 in each manufacturing step;

FIGS. 8A and 8B are schematic diagrams for illustrating a semiconductordevice 200 according to the second embodiment of the present invention;

FIG. 9 is a schematic diagram for illustrating a lead frame 210 used ina semiconductor device 200 according to the second embodiment of thepresent invention;

FIGS. 10A to 12B are schematic diagrams for illustrating the state ineach step for manufacturing a semiconductor device 200 according to thesecond embodiment of the present invention;

FIGS. 13A and 13B are schematic diagrams for illustrating asemiconductor device 300 according to the third embodiment of thepresent invention;

FIG. 14 is a schematic diagram for illustrating a lead frame 310 used inthe semiconductor device 300 in the third embodiment of the presentinvention;

FIGS. 15A and 15B are schematic diagrams for illustrating anothersemiconductor device according to the third embodiment of the presentinvention;

FIG. 16 is a schematic sectional view for illustrating the semiconductordevice 400 according to the fourth embodiment of the present invention;

FIG. 17 is an enlarged side view of the semiconductor device 400according to the fourth embodiment of the present invention.

FIG. 18 is a schematic top view for illustrating a lead frame 410 usedin the semiconductor device 400 in the fourth embodiment of the presentinvention;

FIG. 19 is a flow diagram for illustrating the method for manufacturinga semiconductor device 400 according to the fourth embodiment of thepresent invention;

FIGS. 20 to 22 are schematic diagrams for illustrating the state of thesemiconductor device 400 in each manufacturing step.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The embodiments of the present invention will be described belowreferring to the drawings. In the drawings, the same or correspondingparts will be denoted with the same reference numerals, and thedescription thereof will be simplified or omitted.

First Embodiment

FIGS. 1A and 1B are schematic diagrams for illustrating a semiconductordevice 100 in the first embodiment of the present invention, FIG. 1Aillustrating a cross section and FIG. 1B illustrating a lower surface.

For the convenience of description, the upper surface in FIG. 1A, whichis the major surface side wherein the electrodes of the of semiconductorchip 2 and the like are formed, is referred to as “the front surface”;and the lower surface FIG. 1A is referred to as “the bottom surface”.The direction along to two sides facing up and down on the bottomsurface of the semiconductor device in FIG. 1B is referred to as “thelateral direction”, and the direction perpendicular to the lateraldirection is referred to as “the vertical direction”.

As FIG. 1A illustrates, in the semiconductor device 100, a semiconductorchip 2 is mounted on leads 4 through a die bonding material 6. Bondingpads 8 which are the electrodes on the semiconductor chip 2 areconnected to leads 4, which become terminals in the semiconductor device100, with gold wires 10. The semiconductor chip 2 is sealed with asealing resin 12 in the state thus mounted on the leads 4, and connectedwith gold wires 10. As FIG. 1B illustrates, leads 4 are exposed on thebottom surface of the semiconductor device 100, and each lead 4 issubjected to plating and provided with exterior plating 14.

FIG. 2 is a schematic top view for illustrating a lead frame 110 used inthe semiconductor device 100 in the first embodiment of the presentinvention.

As FIG. 2 illustrates, a plurality of lead patterns are disposed on thelead frame 110. Each of lead pattern is composed of plurality of leads 4which are vertically and laterally disposed on the lead frame 110perpendicularly to each peripheral side of the lead frame 110 in thestate wherein leads 4 do not intersect each other. In each of leadpatterns, four leads 4 located on each of four corners are constitutedto be shorter than others. The rest of leads 4, namely the total of 10leads 4 disposed in the vertical direction, and the total of two leads 4disposed in the lateral direction, are constituted to be longer. Thelong leads 4 are disposed so as to extend from island areas 16, whichare the areas for mounting of semiconductor chips 2, to the peripheralportions of the island areas 16.

In each of the lead patterns, two lines in each of vertical and lateraldirections, namely the total of four lines, become dicing lines 18. Thedicing lines 18 are lines that extend in parallel to each side at thelocation to contact the ends of short leads 4, and long leads 4 are cutin two portions at this location after the semiconductor device issealed with a resin.

In the lead frame 110, the plurality of lead patterns of leads 4 arrayedas described above are constituted side by side, and a semiconductorchip 2 can be mounted on each island area 16.

FIG. 3 is a flow diagram for illustrating the method for manufacturing asemiconductor device 100 according to the first embodiment of thepresent invention. FIGS. 4A to 7B are schematic diagrams forillustrating the state of the semiconductor device 100 in eachmanufacturing step. In each diagram, FIGS. 4A, 5A, 6A and 7A illustratethe cross section, FIGS. 4B, 5B, 6B and 7B illustrate the bottomsurface, and FIG. 5C, illustrates the front surface.

The method for manufacturing the semiconductor device 100 in the firstembodiment of the present invention will be described below in detailreferring to FIGS. 3 to 7.

First, as FIGS. 4A and 4B illustrate, a semiconductor chip 2 is mountedon the island area 16 of a lead frame 110, and fixed with a die-bondingmaterial 6 (Step S2). At this time, the semiconductor chip 2 is overlaidon the long leads 4.

Next, as FIGS. 5A, 5B and 5C illustrate, the bonding pads 8 on thesemiconductor chip 2 are wire-bonded to the leads 4 with gold wires 10(Step 4). An end of a gold wire 10 is connected to each bonding pad 8 ofthe semiconductor chip 2. The other end of the gold wire 10 is connectedto a lead 4. At this time, two gold wires 10 are connected to differentlocations of each long lead 4. On the other hand, one gold wire 10 isconnected to a location of each short lead 4.

Next, as FIGS. 6A and 6B illustrate, in the state wherein bonding pads 8and leads 4 are connected with gold wires 10, the semiconductor chip 2is mold-sealed with a sealing resin 12 on the lead frame 110 (Step S6).Thereby, the semiconductor chip 2 is sealed on the leads 4 of the leadframe 110. At this time, on the bottom surface, the leads 4 are exposedfrom the sealing resin 12 as FIG. 6B illustrates.

Next, long leads 4 among the leads 4 on the bottom surface are cut intwo portions along the dicing lines 18 using a blade (Step S8). Thereby,as FIGS. 7A and 7B illustrate, two bonding pads 8 of the semiconductorchip 2 that have been connected to a long lead 4 are in the statewherein each bonding pad 8 is connected to a cut individual lead 4, andthe short-circuited state is released. In the first embodiment, sincethe dicing lines 18 are in the locations contacting the short leads 4,the short leads 4 are not cut, and stay intact.

Next, each lead 4 is subjected to plating and provided with exteriorplating 14 (Step S10). Thereby, a semiconductor device 100 as shown inFIGS. 1A and 1B is completed.

According to the first embodiment, as described above, long leads 4 andshort leads 4 are disposed on each of lead patterns in the lead frame110 in the state wherein the leads 4 do not intersect each other, andthe long leads 4 can be cut in two portions, and can be used as separateterminals as required. Therefore, one type of lead frame 110 can be usedcorresponding to various semiconductor chips having different numbers ofbonding pads. Therefore, the productivity of lead frames can beimproved, and the cost reduction of semiconductor devices can beachieved.

According to the first embodiment, bonding is performed using long leads4 as they are, and after mold sealing, the long leads 4 are cut.Therefore, in the lead frame 110, it is not required to previously formleads 4 of complicated arrangement patterns to meet individual ofsemiconductor chips. Therefore, the productivity of lead frames can beimproved, and the cost reduction of semiconductor devices can beachieved.

According to the first embodiment, leads 4 are disposed to underneaththe semiconductor chip 2. Therefore, taking the cutting of the leads 4,productivity, and the like into consideration, while securing the lengthof leads 4 to be long, in the lead, which is a portion close to thesemiconductor chip 2 only the space at least required for wire bondingusing gold wires 10 can be taken outside the semiconductor chip 2, andthe unnecessary portion can be disposed in the space underneath thesemiconductor chip 2. Therefore, the space required for the leads 4 canbe minimized as much as possible, and the further miniaturization of thesemiconductor device 100 can be achieved.

In addition, in the first embodiment, the case wherein only long leads 4are cut and divided into two portions is described. However, the presentinvention is not limited thereto, but may include the cases whereinshort leads 4 are cut, or long leads 4 are cut into three portions. Thenumber of cutting operations and the locations of cutting can beadjusted considering the number of terminals required for the number ofbonding pads in the semiconductor chip 2.

Further in the first embodiment, the lead frame 110 having nine leads 4in two columns in the vertical direction, a total of 18 leads, and fiveleads 4 in two rows in the lateral direction, a total of 10 leads; amongwhich four leads 4 located on each of the four corners are shortened,and the rest of the leads 4 are lengthened, is described. However, inthe present invention, the number of the leads 4, the ratio of long andshort leads 4, and the arrangement pattern of the leads 4 are notlimited thereto. The number of the leads 4 or the arrangement pattern ofthe leads 4 may be selected as required, considering the number and thearrangement of bonding pads 8 in the semiconductor chip 2, or the sizeof finally formed semiconductor device 100.

Also in the first embodiment, the case wherein leads 4 are cut using ablade or the like is described. However, the present invention is notlimited to such a cutting method, but other methods, such as etching,may also be used.

Second Embodiment

FIGS. 8A and 8B are schematic diagrams for illustrating a semiconductordevice 200 according to the second embodiment of the present invention;FIG. 8A illustrating a cross section, and FIGS. 8B illustrating thebottom surface. FIG. 8A shows the cross section in the I-I′ direction inFIG. 8B.

As FIGS. 8A and B illustrate, the semiconductor device 200 is similar tothe semiconductor device 100 described in the first embodiment. However,in the semiconductor device 200, the leads 20 are different from leads 4in the lead frame 110 in the first embodiment, and are formed by gridironing a lead plate 22. Each lead 20 is subjected to plating andprovided with exterior plating 14 as in the first embodiment.

FIG. 9 is a schematic diagram for illustrating a lead frame 210 used ina semiconductor device 200 according to the second embodiment of thepresent invention.

As FIG. 9 illustrates, a plurality of lead plates 22 are arrayed on thelead frame 210 used in the second embodiment. Each lead plate 22 has anisland area 24, which is an area for mounting a semiconductor chip 2. Inthe second embodiment, seven lines arranged in each of vertical andlateral directions in a lattice pattern become dicing lines 26, and bycutting along the dicing lines 26, the lead plate 22 is divided intoleads 20 that become individual terminals.

FIGS. 10A to 12B are schematic diagrams for illustrating the state ineach step for manufacturing a semiconductor device 200 according to thesecond embodiment of the present invention. In each drawing, FIGS. 10A,11A and 12A illustrate the cross section, and FIGS. 10B, 11B and 12Billustrate the bottom surface.

The method for manufacturing the semiconductor device 200 in the secondembodiment is the same as the manufacturing method described for thefirst embodiment. However, in the second embodiment, the dicing lines 26are different from dicing lines 18 in the cutting step (Step S10)described for the first embodiment.

The method for manufacturing a semiconductor device 200 in the secondembodiment will be described below referring to FIGS. 2 and 10A to 12B.

First, a semiconductor chip is mounted on an island area 24 of a leadplate 22, and is fixed using a die-bonding material 6 (Step S2). Next,as FIGS. 10A and 10B illustrate, the bonding pads 8 on the semiconductorchip 2 are connected to the lead plate 22 using gold wires 10 (Step S4).Here, an end of a gold wire 10 is connected to each bonding pad 8 of thesemiconductor chip 2. The other end of the gold wire 10 is connected toeach location to subsequently become leads 20 formed by cutting the leadplate 22.

Next, as FIGS. 11A and 11B illustrate, mold sealing using the sealingresin 12 is performed in the state wherein gold wires 10 have beenconnected (Step S6). Thereby, the semiconductor chip 2 is sealed on thelead plate 22. As FIG. 11B illustrates, the lead plate 22 is in anexposed state in the backside of the lead plate 22.

Next, the lead plate 22 is cut along the dicing lines 26 in a latticepattern (Step S8). Thereby, the lead plate 22 is divided into a requirednumber of leads 20. Thereafter, each lead 20 is subjected to plating andprovided with exterior plating 14 (Step S10). Thereby, the semiconductordevice 200 as illustrated in FIGS. 8A and 8B is completed.

According to the semiconductor device 200, as described above, the leadplate 22 is cut to use as leads 20. Therefore, one type of lead plate 22can correspond to a plurality of types of semiconductor chips 2 havingdifferent numbers of electrodes. Thereby, the productivity of leadframes 210 is improved, and the production costs of semiconductor device200 can be lowered.

In the semiconductor device 200, since the lead plate 22 is cut to useas leads 20, no complicated steps for manufacturing the lead frame 210are required. Therefore, the improvement of the productivity of leadframes 210 can be achieved, leading to the reduction of the productioncosts of semiconductor devices.

According to the semiconductor device 200, the lead plate 22 exposed onthe bottom surface can be cut into leads 20. In the lead plate 22, theparts not required for bonding are disposed under the semiconductor chip2, and only the parts required for bonding are disposed outside thesemiconductor chip 2. Thereby, the size of the semiconductor device 200can be reduced.

In the second embodiment, the lead plate 22 is divided into eight rowsand eight columns of leads 20 by seven dicing lines 26 in each ofvertical and lateral directions. However, in the present invention, thenumber of dicing lines 26 is not limited thereto. The number of dicinglines may be selected as required considering the number and arrangementof bonding pads of the semiconductor chip to be mounted. Therefore, itis not required that the number of dicing lines in the verticaldirection is the same as the number of dicing lines in the lateraldirection. Also for example, the area of the lead plate 22 not used asthe terminals of the island area 24 may not be cut.

Since other parts are same as those in the first embodiment, thedescription thereof will be omitted.

Third Embodiment

FIGS. 13A and 13B are schematic diagrams for illustrating asemiconductor device 300 according to the third embodiment of thepresent invention; FIG. 13A illustrating a cross section, and FIG. 13Billustrating the bottom surface. FIG. 14 is a schematic diagram forillustrating a lead frame 310 used in the semiconductor device 300 inthe third embodiment of the present invention. FIGS. 15A and 15B areschematic diagrams for illustrating another semiconductor deviceaccording to the third embodiment of the present invention; FIG. 15Aillustrating a cross section, and FIG. 15B illustrating the bottomsurface.

The semiconductor device 300 shown in FIG. 13 is similar to thesemiconductor device 200 described in the second embodiment. However, inthe semiconductor device 300, there are no leads 30 under thesemiconductor chip 2, and the sealing resin 12 is exposed.

As FIG. 14 illustrates, the lead plates 32 in the lead frame 310 areflat plates each having an opening in the center portion, and theopening becomes the island area 34. Therefore, no portions to be leads30 are formed in the island area 34.

The method for manufacturing a semiconductor device 300 in the thirdembodiment is the same as the method for manufacturing a semiconductordevice 200 described for the second embodiment. However, in the thirdembodiment, a lead frame 310 having island areas 34 wherein no leads 30are formed is used as described above. Therefore, in the mold sealing(Step S6) in the third embodiment, a sealing resin 12 is also injectedinto the portions where no leads 30 are formed. Therefore, as FIGS. 13Aand 13B illustrate, the semiconductor device 300 wherein no leads butthe sealing resin 12 are exposed on the bottom surface of thesemiconductor chip 2.

Thereby, a semiconductor device having the same effect as in the secondembodiment can be obtained.

In the third embodiment, no sealing resin 12 is permeated into portionscut along the dicing lines 36 of the lead frame 310, i.e., the portionssandwiched by leads 30 adjacent to each other. However, a trench may bepreviously formed along the dicing lines 36 on the surface side of thelead frame 310 for injecting the sealing resin 12 into the trench asFIG. 15 illustrates. Thereby the adhesion of the leads 30 and thesealing resin 12 is enhanced, and the reliability of the semiconductordevice 300 can be improved.

Fourth Embodiment

FIG. 16 is a schematic sectional view for illustrating the semiconductordevice 400 in the fourth embodiment of the present invention. FIG. 17 isan enlarged side view of the semiconductor device 400.

As FIG. 16 illustrates, in the semiconductor device 400, a semiconductorchip 2 is mounted on a lead frame 410 using a die-bonding material 6.The bonding pads 8 on the semiconductor chip 2 are connected to theleads 40 to become the terminals in the semiconductor device 400 withgold wires 10. The semiconductor chip 2 is sealed with a sealing resin12 in the state thus mounted on the leads 40 and connected with goldwires 10.

As FIG. 17 illustrates, the marks of the blade are left on the side ofthe semiconductor device 400. The marks of the blade are left when theleads are cut using the blade from up and down. Therefore, the marks ofthe blade are left on the sealing resin 12 due to cutting from the frontand back directions; and the marks of the blade in one direction areleft on the lead frame portion due to cutting from the back direction.

FIG. 18 is a schematic top view for illustrating a lead frame 410 usedin the semiconductor device 400 in the fourth embodiment of the presentinvention.

As FIG. 18 illustrates, three lines of island areas 42 for mountingsemiconductor chips 2 are formed on the lead frame 410. The lead frame410 is cut along chip dicing lines 44 in the vertical and lateraldirections, and finally divided into individual semiconductor devices400.

In the lead frame 410, 16 columns of leads 40 extending in the verticaldirection are formed on the areas between two chip-dicing lines 44 inthe vertical direction. On the other hand, a line of lead 40 extendingin the lateral direction is formed in each of substantial centers ofportions between two chip-dicing lines 44 in the lateral direction.

Two lines in each of the areas between a chip-dicing line 44 in thelateral direction and the lead 40 in the lateral direction becomelead-dicing lines 46. In the entire lead frame 410, there are a total of12 lead-dicing lines 46 in the lateral direction. The lead-dicing lines46 are cutting lines for dividing the lead 40 into leads 40corresponding to the bonding pads 8 in one-to-one manner. On the surfaceside for mounting the semiconductor chips 40, a trench (not shown) of adepth of a half the thickness of the lead frame 410 is previously formedin the location to be the lead dicing line 40.

FIG. 19 is a flow diagram for illustrating the method for manufacturinga semiconductor device 400 according to the fourth embodiment of thepresent invention. FIGS. 20 to 22 are schematic diagrams forillustrating the state of the semiconductor device 400 in eachmanufacturing step.

The method for manufacturing a semiconductor device 400 according to thefourth embodiment of the present invention will be described in detailbelow referring to FIGS. 19 to 22.

First, as FIG. 20 illustrates, a plurality of semiconductor chips 2 aremounted on each island area 42 of the lead frame 410, and are fixedusing a die-bonding material 6 (Step S2). At this time, thesemiconductor chips 2 are mounted on the leads 40 in piles.

Next, the bonding pads 8 on each semiconductor chip 2 and leads 40 arewire-bonded with gold wires 10 (Step 4). At this time, an end of each oftwo gold wires 10 is connected to a portion of each lead 40 in verticaldirection between chip-dicing lines 44 in the vertical direction and theleads 40 in the lateral direction (for convenience, the portion isreferred to as a section of the leads 40) so as not to contact eachother. The other end of each gold wire 10 is connected to a separatebonding pad 8. Specifically in this state, bonding pads 8 areshort-circuited.

Next, the semiconductor chips 2 are subjected to mold sealing on thelead frame 410 with a sealing resin 12 (Step S6). Thereby, thesemiconductor chips 2 are sealed on the lead frame 410. At this time,individual semiconductor chips 2 are not sealed, but the entire surfaceof the lead frame 410 is collectively resin-sealed. On the bottomsurface of the lead frame 410, leads 40 are exposed out of the sealingresin 12. The trenches formed along the lead-dicing lines 46 of the leadframe 410 are also filled with the sealing resin 12.

Next, as FIG. 21 illustrates, the leads 40 are cut in the lateraldirection along the lead-dicing lines 46 using a blade from the side ofthe bottom surface (Step S8). Here, each region between the chip-dicinglines 44 in the lateral direction and the leads 40 in the lateraldirection are cut along two lead-dicing lines 46 in the lateraldirection. Thereby, each lead 40 in each region between two chip-dicinglines 44 in the lateral direction is divided into five portions by fourdicing lines 46. Thereby, the each of the sections of the lead 40 isdivided into independent leads 40. Therefore, each of the two bondingpads 8 that has been connected to one section of the lead 40 is in thestate connected to each of cut individual leads 40, and thesort-circuited state is released. The portion to which leads 40 in thevertical direction are intersecting the lead 40 in the lateral directionis left as it is. However, since no gold wires 10 are connected to thisportion, and the sort-circuited state is also released even in the statewherein this portion is left as it is.

Next, the lead frame 410 is divided along the chip-dicing lines 44 intoindividual semiconductor devices 400 (Step S20). Here, as FIG. 22illustrates, the lead frame 410 is divided along the chip-dicing lines44 in vertical and lateral directions, into individual semiconductordevices 400. At this time, since the total of the lead frame 410 and thesealing resin 12 has a considerable thickness, dicing is performed fromboth the front and back sides of the semiconductor device 400. Thereby,semiconductor devices 400 each having the surface of the sealing resin12 that has the marks of the blade in two directions, and the surface ofthe lead frame 40 that has the marks of the blade in one direction, canbe formed.

Thereafter, each lead 40 is subjected to plating (Step S10). At thistime, the number of leads 40 formed in each semiconductor device 400 andused as terminals is 16×2 in one side, and 16×4 in total. Therefore, itis sufficient to form exterior platings 14 on a total of 64 leads 40.

In the semiconductor device 400, as described above, the lead frame 410is cut to use as the leads 40. Therefore, one type of lead plate 410 cancorrespond to a plurality of types of semiconductor chips 2 havingdifferent numbers of bonding pads 8. Thereby, the productivity of thelead frames 410 can be improved, and the production costs of thesemiconductor devices 400 can be lowered.

In the semiconductor device 400, since the leads 40 are cut, nocomplicated steps for manufacturing the lead frame 410 are required.Therefore, the improvement of the productivity of the lead frame 410 canbe achieved, leading to the reduction of the production costs ofsemiconductor devices.

In the fourth embodiment, each of a plurality of semiconductor chips 2is mounted on each island area 42 on one lead frame, resin sealing orthe like is performed, and after dicing predetermined parts of the leads40, the lead frame is divided into individual semiconductor devices 400.Therefore, the manufacturing steps can be simplified, and the productioncosts can be lowered.

In the fourth embodiment, the case wherein each section of the leads 40is divided into two portions in the lateral direction is described.However, the present invention is not limited thereto, but the number ofcutting operations can be adjusted considering the required number ofterminals for the number of electrodes in the semiconductor chip 2.Here, 16 vertically long leads 40 are formed in a chip, and are cut.However, the number of the leads 40 is not limited thereto. In thepresent invention, for example, the lead frames as described in thefirst to third embodiments can be formed sequentially.

In the fourth embodiment, the case wherein the leads are cut using ablade and the like is described. However, the present invention is notlimited to such a cutting method, but other methods, such as etching,can also be used for cutting. The cutting using a blade is not limitedto cutting both upward and downward, but cutting from one side can alsobe used. The cutting methods can be selected considering the thicknessof the entire semiconductor device.

Also in the fourth embodiment, the case wherein trenches are formed onthe surface of the lead frame 410 for mounting the semiconductor chips 2corresponding to the lead-dicing lines 46 is described. However, thepresent invention is not limited thereto, but for example, no trenchesmay be formed.

Since other parts are same as those in the first to third embodiments,the description thereof will be omitted.

The features and the advantages of the present invention as describedabove may be summarized as follows.

According to one aspect of the present invention, leads in a lead frameused in a molded package can be formed also on the area to mount thesemiconductor chip, and leads in this area can also be utilized asexternal terminals. Therefore, the lead frame can cope with increase inthe number of leads, while suppressing the enlargement of thesemiconductor device.

Another aspect of the present invention, after the leads have beenconnected to the electrodes of the lead frame with gold wires, andsealed with a resin, the leads are cut into individual terminals asrequired. Therefore, one type of lead frame can be used in varioussemiconductor chips having different number of electrodes, and theproductivity of lead frames can be improved. Thereby, the productioncosts can be suppressed low even when the number of leads increases.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay by practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No. 2003-347120,filed on Oct. 6, 2003 including specification, claims, drawings andsummary, on which the Convention priority of the present application isbased, are incorporated herein by reference in its entirety.

1. A lead frame used in the mold package of a semiconductor device,comprising a lead to be terminals in the semiconductor device, whereinsaid lead can be divided by cutting into a plurality of parts that canbe used as terminals.
 2. The lead frame according to claim 1, whereinsaid lead is a plurality of lead wires arrayed in directionsperpendicular to each peripheral side of said lead frame; and at leastone of said lead wires is disposed extending from the area whereon asemiconductor chip is mounted to the exterior of the area.
 3. The leadframe according to claim 1, wherein said lead is plate larger than thelower surface of a semiconductor chip to be mounted.
 4. The lead frameaccording to claim 3, wherein said lead is a plate having an opening inthe location for mounting a semiconductor chip.
 5. A semiconductordevice comprising: a semiconductor chip having a plurality of bondingpads, a lead frame mounting said semiconductor chip, and including alead to become terminals in the semiconductor device, gold wires forelectrically connecting said bonding pads to predetermined locations ofsaid lead, and a sealing member for sealing said semiconductor chip onsaid lead frame, wherein said lead is divided into a predeterminednumber at predetermined locations after mounting said semiconductorchip, and are used as individual terminals corresponding to said bondingpads in a one-to-one manner.
 6. The semiconductor device according toclaim 5, wherein said lead frame has a plurality of mounting portionsfor mounting said semiconductor chip; and said semiconductor device iscomposed by further cutting said sealing member and said lead frameafter dividing said leads, and a part of said sealing member and a partof said lead frame are exposed on the cutting surfaces of saidsemiconductor device.
 7. The semiconductor device according to claim 6,wherein said sealing member exposed on said cutting surfaces has a blademark cut in a plurality of cutting operations, and said lead frameexposed on said cutting surfaces has a blade mark cut in one cuttingoperation.
 8. The semiconductor device according to claim 5, whereinsaid lead is a plurality of lead wires arrayed in directionsperpendicular to each peripheral side of said lead frame; and at leastone of said lead wires is disposed extending from the area whereon saidsemiconductor chip is mounted to the exterior of the area.
 9. Thesemiconductor device according to claim 5, wherein said lead is a platelarger than the lower surface of said semiconductor chip, and saidsemiconductor chip is mounted on said plate.
 10. The semiconductordevice according to claim 9, wherein said lead is a plate having anopening in the location for mounting said semiconductor chip.
 11. Amethod for manufacturing a semiconductor device comprising: a mountingstep for mounting a semiconductor chip that has a plurality of bondingpads on a predetermined location of a lead frame; a connecting step forconnecting said bonding pads to a lead of said lead frame by a goldwire; a sealing step for sealing said semiconductor chip on said leadframe using a sealing member; and a cutting step for cuttingpredetermined locations of said lead frame to divide said lead intoindividual terminals corresponding to said bonding pads in a one-to-onemanner.
 12. The method for manufacturing a semiconductor deviceaccording to claim 11, wherein said lead frame comprises a plurality ofmounting portions for mounting a plurality of semiconductor chips; insaid mounting step, each of said semiconductor chips is mounted on eachof said mounting portion; and said method for manufacturing asemiconductor device further comprises, after said cutting step, adividing step for cutting predetermined locations of said lead frame andsaid sealing member to divide into individual semiconductor devices. 13.The method for manufacturing a semiconductor device according to claim11, wherein said lead is a plurality of lead wires arrayed in directionsperpendicular to each peripheral side of said lead frame; and at leastone of said lead wires is disposed extending from the area whereon saidsemiconductor chip is mounted to the exterior of the area.
 14. Themethod for manufacturing a semiconductor device according to claim 11,wherein said lead is a plate larger than the lower surface of saidsemiconductor chip, and in said cutting step, said lead is cut ingrid-like pattern.
 15. The method for manufacturing a semiconductordevice according to claim 14, wherein said lead is a plate having anopening in the location for mounting said semiconductor chip.